YodaNN: An Architecture for Ultra-Low Power Binary-Weight CNN Acceleration
June 17, 2016 ยท Declared Dead ยท ๐ IEEE Computer Society Annual Symposium on VLSI
"No code URL or promise found in abstract"
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Authors
Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini
arXiv ID
1606.05487
Category
cs.AR: Hardware Architecture
Cross-listed
cs.CV,
cs.NE
Citations
202
Venue
IEEE Computer Society Annual Symposium on VLSI
Last Checked
1 month ago
Abstract
Convolutional neural networks (CNNs) have revolutionized the world of computer vision over the last few years, pushing image classification beyond human accuracy. The computational effort of today's CNNs requires power-hungry parallel processors or GP-GPUs. Recent developments in CNN accelerators for system-on-chip integration have reduced energy consumption significantly. Unfortunately, even these highly optimized devices are above the power envelope imposed by mobile and deeply embedded applications and face hard limitations caused by CNN weight I/O and storage. This prevents the adoption of CNNs in future ultra-low power Internet of Things end-nodes for near-sensor analytics. Recent algorithmic and theoretical advancements enable competitive classification accuracy even when limiting CNNs to binary (+1/-1) weights during training. These new findings bring major optimization opportunities in the arithmetic core by removing the need for expensive multiplications, as well as reducing I/O bandwidth and storage. In this work, we present an accelerator optimized for binary-weight CNNs that achieves 1510 GOp/s at 1.2 V on a core area of only 1.33 MGE (Million Gate Equivalent) or 0.19 mm$^2$ and with a power dissipation of 895 ฮผW in UMC 65 nm technology at 0.6 V. Our accelerator significantly outperforms the state-of-the-art in terms of energy and area efficiency achieving 61.2 TOp/s/W@0.6 V and 1135 GOp/s/MGE@1.2 V, respectively.
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