Loop Summarization with Rational Vector Addition Systems (extended version)
May 16, 2019 ยท Declared Dead ยท ๐ International Conference on Computer Aided Verification
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Authors
Jake Silverman, Zachary Kincaid
arXiv ID
1905.06495
Category
cs.PL: Programming Languages
Citations
21
Venue
International Conference on Computer Aided Verification
Last Checked
1 month ago
Abstract
This paper presents a technique for computing numerical loop summaries. The method synthesizes a rational vector addition system with resets (Q-VASR) that simulates the action of an input loop, and then uses the reachability relation of that Q-VASR to over-approximate the behavior of the loop. The key technical problem solved in this paper is to automatically synthesize a Q-VASR that is a best abstraction of a given loop in the sense that (1) it simulates the loop and (2) it is simulated by any other Q-VASR that simulates the loop. Since our loop summarization scheme is based on computing the exact reachability relation of a best abstraction of a loop, we can make theoretical guarantees about its behavior. Moreover, we show experimentally that the technique is precise and performant in practice.
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