A framework of constructing placement delivery arrays for centralized coded caching
August 16, 2019 Β· Declared Dead Β· π IEEE Transactions on Information Theory
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Authors
Minquan Cheng, Jinyu Wang, Xi Zhong, Qiang Wang
arXiv ID
1908.05865
Category
cs.IT: Information Theory
Cross-listed
math.CO
Citations
46
Venue
IEEE Transactions on Information Theory
Last Checked
6 months ago
Abstract
In caching system, it is desirable to design a coded caching scheme with the transmission load $R$ and subpacketization $F$ as small as possible, in order to improve efficiency of transmission in the peak traffic times and to decrease implementation complexity. Yan et al. reformulated the centralized coded caching scheme as designing a corresponding $F\times K$ array called placement delivery array (PDA), where $F$ is the subpacketization and $K$ is the number of users. Motivated by several constructions of PDAs, we introduce a framework for constructing PDAs, where each row is indexed by a row vector of some matrix called row index matrix and each column's index is labelled by an element of a direct product set. Using this framework, a new scheme is obtained, which can be regarded as a generalization of some previously known schemes. When $K$ is equal to ${m\choose t}q^t$ for positive integers $m$, $t$ with $t<m$ and $q\geq 2$, we show that the row index matrix must be an orthogonal array if all the users have the same memory size. Furthermore, the row index matrix must be a covering array if the coded gain is ${m\choose t}$, which is the maximal coded gain under our framework. Consequently the lower bounds on the transmission load and subpacketization of the schemes are derived under our framework. Finally, using orthogonal arrays as the row index matrix, we obtain two more explicit classes of schemes which have significantly advantages on the subpacketization while the transmission load is equal or close to that of the schemes constructed by Shangguan et al. (IEEE Trans. Inf. Theory, 64, 5755-5766, 2018) for the same number of users and memory size.
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