A Survey of System Architectures and Techniques for FPGA Virtualization
November 18, 2020 ยท The Cartographer ยท ๐ IEEE Transactions on Parallel and Distributed Systems
"No code URL or promise found in abstract"
"Title-pattern auto-detect: A Survey of System Architectures and Techniques for FPGA Virtualization"
Evidence collected by the PWNC Scanner
Authors
Masudul Hassan Quraishi, Erfan Bank Tavakoli, Fengbo Ren
arXiv ID
2011.09073
Category
cs.AR: Hardware Architecture
Cross-listed
cs.DC
Citations
32
Venue
IEEE Transactions on Parallel and Distributed Systems
Last Checked
9 days ago
Abstract
FPGA accelerators are gaining increasing attention in both cloud and edge computing because of their hardware flexibility, high computational throughput, and low power consumption. However, the design flow of FPGAs often requires specific knowledge of the underlying hardware, which hinders the wide adoption of FPGAs by application developers. Therefore, the virtualization of FPGAs becomes extremely important to create a useful abstraction of the hardware suitable for application developers. Such abstraction also enables the sharing of FPGA resources among multiple users and accelerator applications, which is important because, traditionally, FPGAs have been mostly used in single-user, single-embedded-application scenarios. There are many works in the field of FPGA virtualization covering different aspects and targeting different application areas. In this survey, we review the system architectures used in the literature for FPGA virtualization. In addition, we identify the primary objectives of FPGA virtualization, based on which we summarize the techniques for realizing FPGA virtualization. This survey helps researchers to efficiently learn about FPGA virtualization research by providing a comprehensive review of the existing literature.
Community Contributions
Found the code? Know the venue? Think something is wrong? Let us know!
๐ Similar Papers
In the same crypt โ Hardware Architecture
R.I.P.
๐ป
Ghosted
R.I.P.
๐ป
Ghosted
Corona: System Implications of Emerging Nanophotonic Technology
R.I.P.
๐ป
Ghosted
A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
R.I.P.
๐ป
Ghosted
SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
R.I.P.
๐ป
Ghosted
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks
R.I.P.
๐ป
Ghosted