Formalising CXL Cache Coherence

October 21, 2024 ยท Declared Dead ยท ๐Ÿ› International Conference on Architectural Support for Programming Languages and Operating Systems

๐Ÿ‘ป CAUSE OF DEATH: Ghosted
No code link whatsoever

"No code URL or promise found in abstract"

Evidence collected by the PWNC Scanner

Authors Chengsong Tan, Alastair F. Donaldson, John Wickerson arXiv ID 2410.15908 Category cs.AR: Hardware Architecture Cross-listed cs.PL Citations 8 Venue International Conference on Architectural Support for Programming Languages and Operating Systems Last Checked 3 months ago
Abstract
We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English specification. This led to us identifying and proposing fixes to several problems we identified as unclear, ambiguous or inaccurate, some of which could lead to incoherence if left unfixed. Nearly all our issues and proposed fixes have been confirmed and tentatively accepted by the CXL consortium for adoption, save for one which is still under discussion. To validate the faithfulness of our model we performed scenario verification of essential restrictions such as "Snoop-pushes-GO", and produced a fully mechanised proof of a coherence property of the model. The considerable size of this proof, comprising tens of thousands of lemmas, prompted us to develop new proof automation tools, which we have made available for other Isabelle users working with similarly cumbersome proofs.
Community shame:
Not yet rated
Community Contributions

Found the code? Know the venue? Think something is wrong? Let us know!

๐Ÿ“œ Similar Papers

In the same crypt โ€” Hardware Architecture

Died the same way โ€” ๐Ÿ‘ป Ghosted